GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation

This paper presents a novel scheme for mitigating delay degradations in digital circuits due to bias temperature instability (BTI). The method works in two alternating phases. In the first, a greater-than-nominal supply voltage, V_dd,g is used, which causes a task to complete more quickly but causes greater aging than the nominal supply voltage, V_dd,n. In the second, the circuit is power-gated, enabling the BTI recovery phase. We demonstrate, both at the circuit and the architectural levels, that this approach can significantly mitigate aging for a small performance penalty.