Title :
Compiler-directed data cache leakage reduction
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, IL, USA
Abstract :
Leakage energy reduction for caches has been the target of many recent research efforts. In this work, we propose a novel compiler directed approach to reduce the data cache leakage energy by exploiting the program behavior. The proposed approach is based on the observation that only a small potion of data are active at runtime and the program spends a lot of execution time in loops, so a large portion of data cache lines, which are not accessed by the loops, can be placed into leakage control mode to reduce leakage energy consumption. The experimental results show that the proposal approach is comparable to the pure hardware based approach in reducing data cache leakage energy.
Keywords :
cache storage; leakage currents; memory architecture; power consumption; compiler-directed data cache; data cache lines; leakage control; leakage energy consumption; leakage energy reduction; loop granularity; Circuits; Computer Society; Energy consumption; Hardware; Optimizing compilers; Program processors; Proposals; Runtime; Very large scale integration;
Conference_Titel :
VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on
Print_ISBN :
0-7695-2097-9
DOI :
10.1109/ISVLSI.2004.1339566