Title :
Suppression of the hot carrier effect in designing LATID MOS devices based on a new substrate current model
Author :
Yang, J.-J. ; Chou, P.C. ; Chung, S.S. ; Chen, C.-S. ; Lin, M.S.
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
The gate-and-drain fully-overlap LATID (Large-Tilt-Angle Implanted Drain) structure has been proposed recently and been used in submicron MOS device design to suppress the spacer-induced degradation and improve the device current drivability. So far, none has been provided to study quantitatively the hot carrier effect for various device process conditions such as the implantation of n- dosage and angle. A closed form expression of a new and accurate substrate current model is proposed based on the effective electric field concept by considering the overall (2D) electric field distribution within devices, which can be used to explain quantitatively and for predicting the substrate currents of LATID MOS devices. Its utilization in designing a hot carrier resistant device is demonstrated.
Keywords :
CMOS integrated circuits; VLSI; hot carriers; insulated gate field effect transistors; semiconductor device models; 2D electric field distribution; LATID MOS devices; ULSI; effective electric field concept; gate-and-drain fully-overlap LATID; hot carrier effect; hot carrier resistant device; large-tilt-angle implanted drain; submicron device design; substrate current model; Degradation; Electronics industry; Hot carrier effects; Hot carriers; Impact ionization; Industrial electronics; MOS devices; Manufacturing industries; Semiconductor device manufacture; Substrates;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-0978-2
DOI :
10.1109/VTSA.1993.263653
