DocumentCode :
3499881
Title :
Thermal qualification of 3D stacked die structures
Author :
Rencz, Marta
Author_Institution :
Dept. of Electron Devices, Budapest Univ. of Technol. & Econ.
fYear :
2006
fDate :
2-4 Oct. 2006
Firstpage :
1
Lastpage :
8
Abstract :
After an introductory discussion of the thermal issues in stacked die packages in general, two major subjects are discussed in the paper: the qualification of die attach in stacked die structures and the questions of compact thermal modeling. An overview is given about the currently used techniques for the qualification of the die attach for failure analysis in stacked structures. The third part of the paper presents the state-of-the-art and the major issues of compact thermal modeling of stacked die packages. A methodology is suggested for the transient compact modeling of stacked die structures
Keywords :
failure analysis; integrated circuit modelling; integrated circuit packaging; integrated circuit reliability; microassembling; thermal management (packaging); 3D stacked die structures; compact thermal modeling; die attach qualification; failure analysis; stacked die packages; thermal qualification; transient compact modeling; Conducting materials; Conductive films; Electronic packaging thermal management; Electronics packaging; Integrated circuit packaging; Microassembly; Qualifications; Silicon; Thermal management; Thermal resistance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Baltic Electronics Conference, 2006 International
Conference_Location :
Tallinn
ISSN :
1736-3705
Print_ISBN :
1-4244-0414-2
Electronic_ISBN :
1736-3705
Type :
conf
DOI :
10.1109/BEC.2006.311052
Filename :
4100273
Link To Document :
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