Energy-efficient RISC design with on-demand circuit-level timing speculation

This paper presents an energy-efficient RISC design with a novel on-demand timing speculation mechanism, which is implemented with dual timing-relaxed datapaths. The proposed approach significantly reduces the design complexity and the overheads of existing double latching approaches, such as Razor. The design has been implemented and fabricated using the TSMC 65GP technology. Its supply voltage can be lowered to 0.6V for 300MHz operations with only 5.35% timing faults, all of which can be rescued with our proposed mechanism at some extra execution cycles.