Title :
A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS
Author :
Bao, Dan ; Chen, Xubin ; Huang, Yuebin ; Wu, Chuan ; Chen, Yun ; Zeng, Xiao Yang
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fDate :
Jan. 30 2012-Feb. 2 2012
Abstract :
A highly-parallel LDPC decoder architecture for 10Gbase-T applications is designed in this paper. Firstly, we reduce the routing complexity and corresponding power consumption by the proposed decoder architecture based on single routing networks. Secondly, the proposed architecture is designed with pipelined layered scheduling and multi-block parallel decoding, which improves operation speed and removes pipeline stalls in conventional highly-parallel layered scheduling. Thirdly, we trade off between hardware cost and throughput by a digit-serial data-path. Fourthly, an efficient early-termination circuit suitable for layered decoding is designed. The decoder is implemented in 130nm 1P8M CMOS process. The core area is 18.4mm2 with 14% reduction, and the decoding throughput is 9.48Gbps operating at 278MHz and 5 iterations. The tested power consumption is 774mW at 1.2V and 80MHz.
Keywords :
CMOS integrated circuits; block codes; codecs; local area networks; parity check codes; power consumption; scheduling; telecommunication network routing; 10Gbase-T Ethernet; 1P8M CMOS process; decoding; highly-parallel layered scheduling; multiblock parallel decoding; pipelined layered scheduling; power consumption; routing complexity; single-routing layered LDPC decoder; size 130 nm; Complexity theory; Decoding; Iterative decoding; Pipelines; Routing; Throughput;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
Conference_Location :
Sydney, NSW
Print_ISBN :
978-1-4673-0770-3
DOI :
10.1109/ASPDAC.2012.6165020