DocumentCode :
3500748
Title :
An ILP-based obstacle-avoiding routing algorithm for pin-constrained EWOD chips
Author :
Chang, Jia-Wen ; Huang, Tsung-Wei ; Ho, Tsung-Yi
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear :
2012
fDate :
Jan. 30 2012-Feb. 2 2012
Firstpage :
67
Lastpage :
72
Abstract :
Electrowetting-on-dielectric (EWOD) chips have become the most popular actuator particularly for droplet-based digital microfluidic (DMF) systems. In order to enable the electrical manipulations, wire routing is a key problem in designing EWOD chips. Unlike traditional very-large-scale-integration (VLSI) routing problems, in addition to routing-path establishment on signal pins, the EWOD-chip routing problem needs to address the issue of signal sharing for pin-count reduction under a practical constraint posed by limited pin-count supply. Moreover, EWOD-chip designs might incur several obstacles in the routing region due to embedded devices for specific fluidic protocols. However, no existing works consider the EWOD-chip routing with obstacles. To remedy this insufficiency, we propose in this paper the first obstacle-avoiding routing algorithm for pin-constrained EWOD chips. Our algorithm, based on effective integer-linear-programming (ILP) formulation as well as efficient routing framework, can achieve high routability with a low design complexity. Experimental results based on real-life chips with obstacles demonstrate the high routability of our obstacle-avoiding routing algorithm for pin-constrained EWOD chips.
Keywords :
VLSI; drops; integer programming; linear programming; microactuators; microfluidics; network routing; EWOD-chip routing; ILP-based obstacle-avoiding routing algorithm; VLSI routing problems; droplet-based DMF systems; droplet-based digital microfluidic systems; electrical manipulations; embedded devices; fluidic protocols; integer-linear-programming formulation; pin-constrained EWOD chips; pin-constrained electrowetting-on-dielectric chips; pin-count reduction; real-life chips; signal sharing; very-large-scale-integration routing problems; wire routing; Algorithm design and analysis; Electrodes; Pins; Routing; System-on-a-chip; Wires; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
Conference_Location :
Sydney, NSW
ISSN :
2153-6961
Print_ISBN :
978-1-4673-0770-3
Type :
conf
DOI :
10.1109/ASPDAC.2012.6165041
Filename :
6165041
Link To Document :
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