TBNM - transistor-level boundary model for fast gate-level noise analysis of macro blocks

A voltage and current-accurate boundary model is presented for custom and hard macro blocks. For a given hierarchical transistor-level netlist of a digital macro block we identify a small but sufficient subset of transistors that form a boundary netlist for performing fast noise analysis. The model contains layers of the original transistors and parasitics around the block boundary. Therefore it can be used with any noise analysis method, including accurate SPICE simulation. We present definition of the transistor boundary noise model (TBNM) for several types of circuits, the algorithm to extract it efficiently, and how to sensitize the new netlist for on-the-fly simulation or library pre-characterization. The use of TBNM enabled automated noise analysis of designs that include many large custom blocks and embedded memory by speeding up their noise characterization by 2 to 3 orders of magnitude