The statistics of device variations and its impact on SRAM bitcell performance, leakage and stability

It has been recognized that as CMOS technology scales, the accompanied scaling of the conventional 6T-SRAM bitcell require careful assessment of the role of device variations on its stability, electrical performance and leakage. As part of our SRAM design methodology, we have studied the statistics of local and across-wafer variations in bitcell-related parameters by using a series of specialized electrical test structures. The resulting quantification of the device variations are useful towards developing accurate mismatch models that can in turn be used to design not only robust SRAM bitcells but also functionally robust memory arrays wherein the role of bitline leakage and the statistics of ´tail-bits´ are understood