A low-leakage high-speed monotonic static CMOS 64b adder in a dual gate oxide 65-nm CMOS technology

In this paper, we investigate the use of monotonic static CMOS logic within a high performance carry look-ahead adder (CLA) in the context of a 65nm technology with significant leakage. The goal is a good compromise between speed, power, and noise immunity. We compare the monotonic static CMOS 64b CLA with domino and static CMOS adders with respect to speed and power consumption, using a predictive dual gate oxide 65nm technology with significant gate leakage. The comparison shows that monotonic-static CMOS is a potentially useful alternative in such applications. Compared to domino and static CMOS, it can provide advantages in evaluation speed and static power for a set of nominal gates sizes