• DocumentCode
    3501778
  • Title

    Wafer bonding for CMOS integration and packaging

  • Author

    Dragoi, Viorel ; Kurz, F. ; Wagenleitner, T. ; Flotgen, C. ; Mittendorfer, G.

  • fYear
    2012
  • fDate
    13-16 Aug. 2012
  • Firstpage
    166
  • Lastpage
    170
  • Abstract
    The use of CMOS wafers imposes important limitations for W2W (Wafer-to-Wafer) or C2W (Chip-to-Wafer) bonding: low processing temperature (max. 400°C), no mobile ions and extreme cleanliness. Additional to substrates preparation a special focus is directed on cleaning and maintaining the wafers clean during processing. Special cleaning processes were adopted for CMOS-compatible applications. The main challenges raised by CMOS-compatible wafer bonding in terms of processing and process control were identified and process solutions will be presented illustrated with examples.
  • Keywords
    CMOS integrated circuits; semiconductor device packaging; wafer bonding; CMOS compatible application; CMOS compatible wafer bonding; CMOS integration; CMOS wafers; Chip to wafer bonding; packaging; process control; wafer to wafer bonding; Annealing; Bonding; CMOS integrated circuits; Plasmas; Silicon; Surface treatment; Wafer bonding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012 13th International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4673-1682-8
  • Electronic_ISBN
    978-1-4673-1680-4
  • Type

    conf

  • DOI
    10.1109/ICEPT-HDP.2012.6474592
  • Filename
    6474592