Title :
Efficient signal integrity verification method of multi-coupled RLC interconnect lines with asynchronous circuit switching
Author :
Je, Taeyong ; Eo, Yungseon
Author_Institution :
Dept. of Electr. & Comput. Eng., Hanyang Univ., Kyunggido
Abstract :
A new signal integrity verification method of integrated circuit interconnects with asynchronous circuit switching is presented. A ramp input is modeled with delayed step inputs. Then signal transient variations due to asynchronous input signal switching are accurately as well as efficiently determined by using traveling-wave-based waveform approximation (TWA) technique. It is shown that using 90nm technology, the signal timing and crosstalk of multi-coupled lines with asynchronous switching inputs have an excellent agreement with SPICE simulation but its computation time is several thousand times faster than that of SPICE simulation using generic segment-based RLC circuit model
Keywords :
RLC circuits; asynchronous circuits; circuit switching; integrated circuit interconnections; integrated circuit modelling; integrated logic circuits; waveform analysis; 90 nm; RLC interconnect lines; SPICE simulation; TWA technique; asynchronous circuit switching; asynchronous input signal switching; integrated circuit interconnects; multi-coupled lines; ramp input; segment-based RLC circuit model; signal integrity verification method; signal timing; traveling-wave-based waveform approximation technique; Asynchronous circuits; Circuit simulation; Computational modeling; Crosstalk; Delay; Integrated circuit interconnections; Integrated circuit technology; SPICE; Switching circuits; Timing;
Conference_Titel :
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2523-7
DOI :
10.1109/ISQED.2006.57
