Title :
Low power units for the Viterbi decoder
Author :
Ghoneima, Maged ; Sharaf, K. ; Ragai, Hani F. ; Zekry, Abd El-Halim
Author_Institution :
Electron. & Commun. Eng. Dept., Ain Shams Univ., Cairo, Egypt
Abstract :
In this paper, the issues of designing a low power VLSI implementation of the Viterbi decoder are addressed. We propose a new improvement in the VLSI architecture of the Add-Compare-Select unit (ACSU) and the State-Decode Unit (SDU) in the Viterbi decoder. These new schemes have led to a 47.6% and 43.9% power consumption reduction compared to the conventional ACSU and SDU architectures, respectively. These new improvements have also reduced the critical path of both units. The use of these new architectures in the design of a systolic sliding block Viterbi decoder, has led to a reduction of 25.8% in power consumption and 12.2% in die area. A 7.3% gain in decoding rate has also been gained without any degradation in error performance
Keywords :
CMOS logic circuits; Viterbi decoding; block codes; integrated circuit design; low-power electronics; systolic arrays; 0.8 micron; 10 MHz; 3.3 V; AMS 0.8 μm CMOS library; VLSI architecture; Viterbi decoder; add-compare-select unit; critical path; decoding rate; error performance; low power VLSI implementation; power consumption reduction; state-decode unit; systolic sliding block Viterbi decoder; Convolutional codes; Decoding; Degradation; Design engineering; Energy consumption; Performance gain; Power engineering and energy; Samarium; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.951671
