DocumentCode :
3507057
Title :
Applying Partial Reconfiguration to Networks-On-Chips
Author :
Pionteck, Thilo ; Koch, Roman ; Albrecht, Carsten
Author_Institution :
Inst. of Comput. Eng., Lubeck Univ.
fYear :
2006
fDate :
28-30 Aug. 2006
Firstpage :
1
Lastpage :
6
Abstract :
This paper presents CoNoChi, an adaptable network-on-chip for dynamically reconfigurable hardware designs. CoNoChi is designed for taking advantage of the partial dynamic reconfiguration capabilities of modern FPGAs and applies this feature to adapt the network structure to the location, number and size of currently configured hardware modules. The network consists of the minimal number of switches required. Switches can be added or removed from the network by a global control instance at runtime. Compared to common fixed network-on-chip structures, the CoNoChi architecture reduces the area requirements and latency of the network and eases the online placement of hardware modules. Two variants of CoNoChi are presented: one is based on a homogeneous hardware structure that is dynamically reconfigurable on logic block level, and the other one is adapted to the limited partial reconfiguration capabilities of Xilinx Virtex-II (Pro) FPGAs
Keywords :
field programmable gate arrays; logic design; network-on-chip; reconfigurable architectures; CoNoChi architecture; Xilinx Virtex-II FPGA; configured hardware modules; dynamically reconfigurable hardware designs; field programmable gate arrays; homogeneous hardware structure; logic block level; networks-on-chips; partial dynamic reconfiguration; Communication networks; Computer networks; Delay; Field programmable gate arrays; Hardware; Network-on-a-chip; Prototypes; Routing protocols; Runtime; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
Conference_Location :
Madrid
Print_ISBN :
1-4244-0312-X
Type :
conf
DOI :
10.1109/FPL.2006.311208
Filename :
4100970
Link To Document :
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