High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs

In this paper we address the high-level synthesis of multiple word-length DSP algorithms over programmable devices (FPGAs). Previous approaches tend to simplify the set of resources, thus alleviating the complexity of the high-level synthesis, but leading to non-optimal solutions. Here, we present a high-level synthesis framework that overcomes these limitations by means of considering: (i) both logic-based and embedded multipliers, (ii) both constant and generic multipliers and (iii) variable latency resources. A simulated annealing based approach for the combined scheduling, resource allocation and binding tasks is presented. When compared to previous approaches, area improvements of up to 60% are reported