ESD performance optimization of ballast resistor on power AlGaAs-GaAs heterojunction bipolar transistor technology

Author

Chu, Charles Y. ; Li, G.P. ; Ho, W.J. ; Hsu, H.Y. ; Kao, T.-M. ; Hua, C. ; Day, Ding

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA

fYear

1999

fDate

28-30 Sept. 1999

Firstpage

235

Lastpage

240

Abstract

Key parameters in power heterojunction bipolar transistor (HBT) ESD design are identified. ESD survivability under forward bias stress is significantly affected by the ballast resistor design, while under reverse bias, it is the peak stress current. Optimization of the design of ballast resistors should enhance both forward and reverse bias stress performance.

Keywords

III-V semiconductors; aluminium compounds; electrostatic discharge; gallium arsenide; heterojunction bipolar transistors; optimisation; power bipolar transistors; protection; resistors; semiconductor device reliability; semiconductor device testing; AlGaAs-GaAs; ESD performance optimization; ESD survivability; ballast resistor; ballast resistor design; ballast resistor design optimization; forward bias stress; forward bias stress performance; peak stress current; power AlGaAs-GaAs heterojunction bipolar transistor technology; power HBT ESD design; power heterojunction bipolar transistor ESD design; reverse bias stress; reverse bias stress performance; Electronic ballasts; Electrostatic discharge; Fingers; Frequency; Gallium arsenide; Heterojunctions; Optimization; Resistors; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999

Conference_Location

Orlando, FL, USA

Print_ISBN

1-58637-007-X

Type

conf

DOI

10.1109/EOSESD.1999.819066

Filename

819066