Title :
Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling
Author :
Chandrasekaran, S. ; Amira, A.
Author_Institution :
Dept. of Electron. & Comput. Eng., Sch. of Eng. & Design Brunei Univ., West London
Abstract :
A framework for power optimisation on FPGA based designs at various functional levels, and high level power estimation methodologies have been presented in this paper. Results obtained are very promising and the developed framework can be employed to power down the FPGA, estimate and model the power for other parameterisable IP cores
Keywords :
field programmable gate arrays; industrial property; FPGA implementations; IP cores; high level modelling; high level power estimation; power optimisation; power reduction; Design engineering; Design optimization; Energy consumption; Field programmable gate arrays; Frequency; Logic devices; Pipeline processing; Power engineering and energy; Power engineering computing; Voltage;
Conference_Titel :
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
Conference_Location :
Madrid
Print_ISBN :
1-4244-0312-X
DOI :
10.1109/FPL.2006.311363
