An architecture and interface for VLSI sensors

A VLSI sensor interface was designed for use in bus-organized sensor-driven process control systems where high accuracy and high reliability are important. The interface permits 12-b digital sensor data to be communicated to the host processor over a bidirectional parallel data bus which includes parity checking. The sensor can be self-testing and uses digital compensation of cross-parameter sensitivities. The interface has been implemented using discrete commercial components and has been designed in monolithic form in 3- mu m single-metal double-poly CMOS technology. The chip has a die area of 10.8 mm*8.5 mm before compaction and has a simulated power dissipation of 75 mW. The on-chip microprocessor operates at 4 MHz and the 12-bit ADC (analog-to-digital converter) has a conversion time of 14 mu s.<>