FPGA based on-chip memory for data dependent applications

To reduce external memory access latency and power in embedded applications, frequently re-used data is identified and buffered in on-chip memory. This paper presents an approach to on-chip memory sub-system architecture for data dependent image processing algorithm. The proposed memory architecture is capable of re-using the data and reduces the external memory access latency. It is implemented and tested with Quad tree Structured Difference Pulse Code Modulation (QSDPCM) algorithm, which involves data dependency. The performance of the proposed memory architecture is compared with Scratch Pad Memory (SPM) for its efficiency. It is observed that the proposed architecture show a better performance compared to SPM.