A methodology for optimizing the FPGA implementation of industrial control systems

When used for concurrent hardware implementation, field-programmable gate arrays (FPGAs) allows the use of numerous operational units such as multipliers and adders in order to implement control systems. However, when short sampling periods are utilized, scheduling with resource constraints and sharing aimed at reducing the required resources can be necessary. This is especially true in systems where the used sampling period is greater than the computation time delay. The aim of this paper is to present a methodology based on FPGA implementation with resource constraints applied to the implementation of Second Order Generalized Integrators (SOGIs) used in power converters. A systematic way of converting a Simulink specification into VHDL code is described which mainly involves customized fixed-point hardware definition, Data Flow Graph (DFG) extraction, Algorithm State Machine with Data path (ASMD) representation and VHDL specification of the system, inter alia.