A load-pull-based behavioral model for Doherty PA design

A fundamental-only behavioral model is extracted from DUT-level swept power load-pull data that is capable of accurately predicting output power, gain and efficiency of high power RF transistors as a function of input drive level, load impedances, frequency and gate bias. The model is implemented with a sub-set of the X-parameter components and is easily ported to modern CAD tools as an X-parameter file. It provides a convenient method for evaluating the performance of RF power transistors in different Doherty PA architectures and can be used to design and optimize matching network, phasing lines and dynamic load modulation for efficient Doherty operation. The model was used to design a symmetric LDMOS DPA with first-pass success, that achieved 55% drain efficiency at average power of 45 dBm with 62dBc ACPR after DPD correction using a 4-C GSM, 6.2 dB PAR signal at 1.842 GHz.