FPGA implementation of a faithful polynomial approximation for powering function computation

Author

Pineiro, J.-A. ; Bruguera, J.D. ; Muller, J.-M.

Author_Institution

Dept. of Electr. & Comput. Eng., Santiago de Compostela Univ., Spain

fYear

2001

fDate

2001

Firstpage

262

Lastpage

269

Abstract

A FPGA implementation of a method for the calculation of faithfully rounded single-precision floating-point powering (X^p) is presented in this paper. A second-degree minimax polynomial approximation is used, together with the employment of table look-up, a specialized squaring unit and a fused accumulation tree. The FPGA implementation of an architecture with a latency of 3 cycles and a throughput of one result per cycle has been performed using a Xilinx XC4036XL device. The implemented unit has an operation frequency over 33 MHz

Keywords

field programmable gate arrays; floating point arithmetic; polynomial approximation; table lookup; FPGA implementation; Xilinx XC4036XL device; faithful polynomial approximation; floating-point powering; function computation; fused accumulation tree; latency; minimax polynomial approximation; operation frequency; squaring unit; table look-up; Computer architecture; Delay; Employment; Field programmable gate arrays; Frequency; Hardware; Polynomials; Power engineering computing; Software performance; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital Systems Design, 2001. Proceedings. Euromicro Symposium on

Conference_Location

Warsaw

Print_ISBN

0-7695-1239-9

Type

conf

DOI

10.1109/DSD.2001.952292

Filename

952292