DocumentCode :
3515406
Title :
An assessment of FPGA suitability for implementation of real-time motion estimation
Author :
Ryszko, Andrzej ; Wiatr, Kazimierz
Author_Institution :
Inst. of Electron., AGH Tech. Univ. of Cracow, Poland
fYear :
2001
fDate :
2001
Firstpage :
364
Lastpage :
367
Abstract :
Motion estimation is very computational demanding operation during video compression process, thus special hardware architectures are required to achieve real-time compression performance. Advantages in increasing complexity, density and speed of programmable logic devices will soon allow us to implement this kind of application specific processors within one programmable chip. This paper evaluates the performance of Block Matching hardware architectures implemented in Xilinx FPGA. Systolic arrays for Full Search algorithm inferred by Komarek and Pirsch (1989) have been implemented and evaluated by achieved clock rate and number of occupied FPGA resources. Results show that with 2D type systolic arrays it is possible to achieve real-time performance of motion estimation for CIF images even with moderate capacity (250 k gates) FPGA chip
Keywords :
data compression; field programmable gate arrays; motion estimation; systolic arrays; video coding; Block Matching hardware architectures; FPGA suitability; Full Search algorithm; Xilinx FPGA; application specific processors; hardware architectures; programmable logic devices; real-time compression performance; real-time motion estimation; systolic arrays; video compression process; Clocks; Computer architecture; Field programmable gate arrays; Hardware; Motion estimation; Signal processing algorithms; Synchronization; Systolic arrays; Throughput; Video compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital Systems Design, 2001. Proceedings. Euromicro Symposium on
Conference_Location :
Warsaw
Print_ISBN :
0-7695-1239-9
Type :
conf
DOI :
10.1109/DSD.2001.952332
Filename :
952332
Link To Document :
بازگشت