DocumentCode :
3515449
Title :
Reliability and thermal assessment of stacked chip-on-metal panel based package (PBP™) with fan-out capability
Author :
Wei, Hsiu-Ping ; Yew, Ming-Chih ; Wu, Chung-Jung ; Chiang, Kuo-Ning
Author_Institution :
Dept. of Power Mech. Eng., Nat. Tsing Hua Univ., Hsinchu
fYear :
2008
fDate :
1-4 Sept. 2008
Firstpage :
327
Lastpage :
332
Abstract :
In this paper, a chip-on-metal (COM) panel based package (PBPtrade) with stacking and fan-out capabilities is proposed. The basic structure of the proposed COM PBPTM contains a bare die back-sided attached to a metallic chip carrier and surrounded by polymer material. As such, the solder bumps could be located on both the surface of the filler polymer and on the chip by introducing redistribution lines. The I/O pads on the chip could also be fanned-out. In the stacked COM PBPtrade, two kinds of via through holes (VTH) are developed as the electrical interconnection between each stacked package. To assess the thermal performance and thermo-mechanical characteristic of the proposed PBPtrade, parametric analysis is performed to investigate the reliability characteristics and thermal performance by finite element analysis (FEA). Factorial design with the analysis of variance (ANOVA) was also conducted to obtain the sensitivity information and interaction relationship of each parameters. The results show that the thickness of the dielectric plays the most important role in reliability performance. It was also observed that the thickness of the chip and adhesive influence the reliability significantly. In terms of thermal performance, the metallic chip carrier can rapidly dissipate the heat generated from the chip and factorial analysis has indicated that it has high sensitivity in the proposed packaging. Based on the reliability and thermal performance assessment, the design guidelines of the COM PBPtrade and stacked PBPtrade are established in this study.
Keywords :
finite element analysis; integrated circuit reliability; solders; system-in-package; thermal analysis; thermal management (packaging); I/O pads; analysis of variance; electrical interconnection; fan-out capability; filler polymer; finite element analysis; metallic chip carrier; parametric analysis; polymer material; reliability characteristics; sensitivity information; solder bumps; stacked chip-on-metal panel based package; system-on-chip; thermal assessment; thermo-mechanical characteristic; via through holes; Analysis of variance; Dielectrics; Finite element methods; Inorganic materials; Packaging; Performance analysis; Polymers; Stacking; Thermal factors; Thermomechanical processes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics System-Integration Technology Conference, 2008. ESTC 2008. 2nd
Conference_Location :
Greenwich
Print_ISBN :
978-1-4244-2813-7
Electronic_ISBN :
978-1-4244-2814-4
Type :
conf
DOI :
10.1109/ESTC.2008.4684370
Filename :
4684370
Link To Document :
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