DocumentCode
3515757
Title
Hardware Discrete Channel Emulator
Author
Boutillon, Emmanuel ; Tang, Yangyang ; Marchand, Cedric ; Bomel, Pierre
Author_Institution
Lab.-STICC, Univ. Eur. de Bretagne, Lorient, France
fYear
2010
fDate
June 28 2010-July 2 2010
Firstpage
452
Lastpage
458
Abstract
In this paper, the emulation environment named Hardware Discrete Channel Emulator (HDCE) has been developed as a coherent framework to emulate on a hardware device (FPGA as the implementation platform in the verification) and simulate on a computer the effect of an Additive White Gaussian Noise (AWGN) in a base band channel. The HDCE is able to generate more than 180 M samples per second for a very low hardware cost, which has been achieved in an efficient architecture. Using the HDCE, the performance evaluation of a coding scheme for a BER of 10−9 requires only one minute of emulation time.
Keywords
Bit error rate; Decoding; Hardware; Indexes; Parity check codes; Random variables; Signal to noise ratio; Additive White Gaussian Noise; BER/FER performance evaluation; Channel emulation; Monte-Carlo simulation; Synthesis; VHDL;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing and Simulation (HPCS), 2010 International Conference on
Conference_Location
Caen, France
Print_ISBN
978-1-4244-6827-0
Type
conf
DOI
10.1109/HPCS.2010.5547099
Filename
5547099
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