DocumentCode :
3516410
Title :
TSV process using bottom-up Cu electroplating and its reliability test
Author :
Chang, H.H. ; Shih, Y.C. ; Hsu, C.K. ; Hsiao, Z.C. ; Chiang, C.W. ; Chen, Y.H. ; Chiang, K.N.
Author_Institution :
Ind. Technol. Res. Inst., Hsinchu
fYear :
2008
fDate :
1-4 Sept. 2008
Firstpage :
645
Lastpage :
650
Abstract :
TSV (through silicon via) is a core technology in 3D IC package. The micro vias can be made by etching or laser drilling. Standard processes for TSV filling begin with seed layer deposition, followed by blind vias copper electroplating. If the aspect ratio of the TSV is higher than 5:1, the costly MOCVD process needs to be used to deposit the seed layer with good step coverage. A special designed electroplating machine and solution for high aspect ratio copper electroplating is needed. Some researchers even use PRP (periodic reverse plating) for void free copper electroplating instead of traditional DC power supply.
Keywords :
bonding processes; copper; electroplating; elemental semiconductors; etching; gold; integrated circuit interconnections; integrated circuit packaging; laser beam machining; masks; scanning electron microscopy; semiconductor device reliability; silicon; 3D IC package; Au; Cu; ICP process; MOCVD; PCB; SEM inspection; TSV process; bonding process; electroplating machine; etch mask; etching; high aspect ratio copper electroplating; laser drilling; micro vias; periodic reverse plating; reliability test; seed layer deposition; sputtered dummy wafer; through silicon via; Copper; Drilling; Etching; Filling; Integrated circuit packaging; MOCVD; Silicon; Testing; Three-dimensional integrated circuits; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics System-Integration Technology Conference, 2008. ESTC 2008. 2nd
Conference_Location :
Greenwich
Print_ISBN :
978-1-4244-2813-7
Electronic_ISBN :
978-1-4244-2814-4
Type :
conf
DOI :
10.1109/ESTC.2008.4684427
Filename :
4684427
Link To Document :
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