Fabrication process for a novel high speed coplanar-to-coaxial off-chip interconnect

In this paper, we present the design and fabrication of a novel chip-to-chip interconnect scheme for use in system-in-package applications. The interconnect system uses an etched trench at the edge of a standard silicon substrate to interface a miniature coaxial cable to the on-chip surface metal layers. This system delivers a shielded, matched impedance transmission path by using a coplanar structure on-chip and a coaxial structure between chips. This system is designed to be compatible with typical perimeter bonded pad sizing and spacing such that the coplanar-to-coaxial transition can be selectively added to a standard wire bond process on high-speed nets.