Title :
ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology
Author :
Ker, Ming-Dou ; Wu, Chung-Yu ; Chang, Hun-Hsien ; Huang, Chien-Chang ; Wu, Chau-Neng ; Yu, Ta-Lee
Author_Institution :
Integrated Circuits & Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique, ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS ICs can be effectively improved
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; ESD current distribution; ESD reliability; capacitor-couple efficiency; deep-submicron low-voltage CMOS IC; gate oxide; on-chip ESD protection circuit; timing-original design model; Breakdown voltage; CMOS integrated circuits; CMOS process; CMOS technology; Electrostatic discharge; Industrial electronics; Integrated circuit technology; MOS devices; Protection; Stress;
Conference_Titel :
Electron Devices Meeting, 1996., IEEE Hong Kong
Print_ISBN :
0-7803-3091-9
DOI :
10.1109/HKEDM.1996.566328
