Fault Diagnosis in Integrated Circuits with BIST

This paper presents an optimized fault diagnosing procedure applicable in built-in self-test environments. Instead of the known approach based on a simple bisection of patterns in pseudorandom test sequences, we propose a novel bisection procedure where the diagnostic weight of test patterns is taken into account. Another novelty is the sequential nature of the procedure which allows pruning the search space. Opposite to the classical approach which targets all failing patterns, in the proposed method not all failing patterns are needed to be fixed for diagnosis. This allows to tradeoff the speed of diagnosis with diagnostic resolution. The proposed method is compared with three known fault diagnosis methods: classical binary search, doubling and jumping. Experimental results demonstrate the advantages of the proposed method compared to the previous ones.