DocumentCode :
3517345
Title :
Hierarchical Identification of Untestable Faults in Sequential Circuits
Author :
Raik, Jaan ; Ubar, Raimund ; Krivenko, Anna ; Kruus, Margus
Author_Institution :
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia
fYear :
2007
fDate :
29-31 Aug. 2007
Firstpage :
668
Lastpage :
671
Abstract :
Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability identification operate at the logic-level and, thus, the methods do not scale. Current paper points out a new class of sequentially untestable faults, called register input logic stuck-on faults. We show that it is possible to identify such faults from the register-transfer level (RTL) description of the circuit. Moreover, we prove by experiments that the considered faults form a large subclass of all the untested faults.
Keywords :
fault diagnosis; sequential circuits; logic-level operation; register-transfer level; sequential test pattern generation; untestability identification; untestable fault hierarchical identification; Automata; Automatic test pattern generation; Automatic testing; Circuit faults; Fault diagnosis; Logic; Registers; Sequential analysis; Sequential circuits; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
Conference_Location :
Lubeck
Print_ISBN :
978-0-7695-2978-3
Type :
conf
DOI :
10.1109/DSD.2007.4341539
Filename :
4341539
Link To Document :
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