Title :
Online Protocol Testing for FPGA Based Fault Tolerant Systems
Author :
Tobola, Jiri ; Kotasek, Zdenek ; Korenek, Jan ; Martinek, Tomas ; Straka, Martin
Author_Institution :
Fac. of Inf. Technol., Brno Univ. of Technol., Bozetechova, Czech Republic
Abstract :
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be performed - in the paper the lowest level is presented. The definition of dedicated language for the description of possible communication faults is presented. The core generator is used to produce VHDL code describing the behaviour of the checker.
Keywords :
fault tolerance; field programmable gate arrays; hardware description languages; logic testing; protocols; FPGA; VHDL code; automated design; communication faults; communication protocol testing; core generator; fault tolerant systems; online protocol testing; Automatic testing; Circuit faults; Circuit testing; Design methodology; Fault detection; Fault tolerant systems; Field programmable gate arrays; Hardware; Protocols; System testing;
Conference_Titel :
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
Conference_Location :
Lubeck
Print_ISBN :
978-0-7695-2978-3
DOI :
10.1109/DSD.2007.4341541
