Author :
Shahidi, G. ; Ajmera, A. ; Assaderaghi, F. ; Bolam, Ronald ; Bryant, A. ; Coffey, M. ; Hovel, H. ; Lasky, J. ; Leobandung, E. ; Lo, H.-S. ; Maloney, M. ; Moy, D. ; Rausch, W. ; Sadana, D. ; Schepis, D. ; Sherony, M. ; Sleight, J.W. ; Wagner, L.F. ; Wu, K.
Author_Institution :
Adv. Silicon Technol., IBM Corp., Hopewell Junction, NY, USA
Abstract :
Partially-depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the same lithography. In this paper, the challenges of mainstreaming the SOI technology in device, material, technology and circuit terms are described.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit manufacture; integrated circuit technology; lithography; silicon-on-insulator; SOI circuits; SOI devices; SOI materials; SOI technology; Si-SiO/sub 2/; bulk technology; lithography; mainstream technology; partially-depleted SOI CMOS technology; performance gain; Bonding; CMOS technology; Circuits; Lithography; Microelectronics; Performance gain; Qualifications; Silicon; Ultra large scale integration; Voltage;
