Title :
A low power /spl Sigma//spl Delta/ analog-to-digital modulator with 50 MHz sampling rate in a 0.25 /spl mu/m SOI CMOS technology
Author :
Swaminathan, A. ; Fong, N. ; Lauzon, P. ; Hong-Kui Yang ; Maliepaard, M. ; Plett, Calvin ; Snelgrove, M.
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Abstract :
A second-order double-sampled analog-to-digital /spl Sigma//spl Delta/ modulator is implemented in a 0.25 /spl mu/m fully-depleted silicon-on-insulator (FDSOI) CMOS process. FDSOI has a better subthreshold swing and reduced short-channel effect compared to traditional bulk CMOS, and therefore the threshold voltage and hence the supply voltage can be lowered for low power applications.
Keywords :
CMOS integrated circuits; integrated circuit design; low-power electronics; sigma-delta modulation; signal sampling; silicon-on-insulator; 0.25 micron; 50 MHz; SOI CMOS technology; Si-SiO/sub 2/; fully-depleted silicon-on-insulator CMOS process; low power applications; low power sigma-delta analog-to-digital modulator; sampling rate; second-order double-sampled analog-to-digital sigma delta modulator; short-channel effect; subthreshold swing; supply voltage; threshold voltage; Content addressable storage; Delta modulation; Inverters; Power amplifiers; Power generation; Sampling methods;
Conference_Titel :
SOI Conference, 1999. Proceedings. 1999 IEEE International
Conference_Location :
Rohnert Park, CA, USA
Print_ISBN :
0-7803-5456-7
DOI :
10.1109/SOI.1999.819835
