A unified synapse-neuron building block for hybrid VLSI neural networks

Author

Djahanshahi, H. ; Ahmadi, M. ; Jullien, G.A. ; Miller, W.C.

Author_Institution

Dept. of Electr. Eng., Windsor Univ., Ont., Canada

Volume

3

fYear

1996

fDate

12-15 May 1996

Firstpage

483

Abstract

This paper presents a hybrid VLSI technique for implementation of multi-layer neural networks using a unified synapse-neuron building block. A new building block is proposed by integrating a partial S-shape neural nonlinearity within a Multiplying DAC. Circuit techniques are used to generate S-shape neural function from the combination of quadratic characteristics of four MOS devices. The proposed architecture offers design modularity and scalability, silicon area efficiency, reduced interconnection problem and increased robustness

Keywords

VLSI; mixed analogue-digital integrated circuits; neural chips; neural net architecture; MOS device; S-shape nonlinear function; architecture; circuit design; hybrid VLSI; interconnection; modularity; multilayer neural network; multiplying DAC; quadratic characteristics; robustness; scalability; silicon area efficiency; unified synapse-neuron building block; Circuit simulation; Digital-analog conversion; Integrated circuit interconnections; MOS devices; Mirrors; Multi-layer neural network; Neural networks; Neurons; Shape; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.541638

Filename

541638