Forecasting Final/Class Yield Based on Fabrication Process E-Test and Sort Data

This paper presents an application of data mining using gradient boosting trees to predict class test yield performance at high volume manufacturing (HVM) based on e-test and sort ancestry parameters. The paper also presents a framework for the predictive capability system and highlights some of the techniques and implementation details. Modeling at wafer level was found to give the best accuracy and the analytic model provides wafer level yield accuracy at 97% within plusmn2% accuracy level for Intel chipset products. Certain functional bins that correlate to e-test and sort can also be modeled for identification of possible high fallouts. In addition, the modeling process also produced Pareto analysis reports that lists dominant influencers and the dependency plots, enabling Assembly and Test (ATM) engineers to feedback to upstream operation engineers. The overall predictive capability has set a new standard for proactive yield monitoring and excursion management at Intel ATM factories and it is useful to various functions including the yield engineering, product engineering, manufacturing and planning.