Analysis of coupled simultaneous switching noise induced from power delivery network in adjacent switching circuit

This paper investigates the estimation of the coupled simultaneous switching noise (SSN) induced from power delivery networks (PDNs) in memory test boards. When the signal changes its reference plane in the board, voltage fluctuation occurs that induces the SSN in the PDN. This induced SSN affects other signals in the test board, reducing signal quality and test reliability. To avoid this problem, precise analysis and modeling become necessary. To demonstrate the analysis model, we designed and fabricated a 6-layer printed circuit board (PCB) on which 11 clock buffers (noise sources) and signal traces (victim lines) were installed. The scattering parameters were measured from 10 MHz to 3 GHz, and the signals in the victim lines were also measured using 20 GHz bandwidth oscilloscope. The PDN impedances and transfer characteristics with/without decoupling capacitors were simulated using both full-wave and circuit simulations, which coincide quite well with the measured data. Finally, we confirm the validity of the proposed simulation model, and we propose a design methodology to minimize the coupled SSN by installing decoupling capacitors on the test board.