Quality and reliability challenges for ultra mobile computing and communication application processor packaging

Author

He, Dongming ; Kang, Wonjae

Author_Institution

Quality & Reliability Eng., Intel Corp., Folsom, CA, USA

fYear

2009

fDate

10-13 Aug. 2009

Firstpage

1104

Lastpage

1112

Abstract

Market drivers, technology scaling and integration trends of application processor packaging are first presented. Component level and board level quality and reliability challenges are then discussed in the areas of thin die and thin core package warpage, lead free flip chip die to package interconnect mechanical integrity, and lead free package to motherboard solder joint reliability. Challenges from package qualification methodology and use condition are also addressed.

Keywords

chip scale packaging; chip-on-board packaging; flip-chip devices; reliability; solders; board level quality; communication application processor packaging; component level; lead free flip chip die; lead free package; motherboard solder joint reliability; package interconnect mechanical integrity; reliability; thin core package warpage; thin die; ultramobile computing; Computer applications; Electronics packaging; Environmentally friendly manufacturing techniques; Hazardous materials; Internet; Mobile communication; Mobile computing; Semiconductor device packaging; Silicon; Smart phones;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Packaging Technology & High Density Packaging, 2009. ICEPT-HDP '09. International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-4658-2

Electronic_ISBN

978-1-4244-4659-9

Type

conf

DOI

10.1109/ICEPT.2009.5270594

Filename

5270594