Short locking time FLL and PLL based on a DLL technique

We propose a new circuit technique dedicated to improve the performance of the frequency and phase locked loops (FLLs & PLLs). The presented technique is based on the use of a delay-locked loop (DLL) to improve the speed of the basic architecture of an FLL or a PLL. The DLL is designed to lock on the input reference frequency and its control voltage is used to bias the voltage-controlled oscillator (VCO) of the FLL or the PLL. Since the DLL is unconditionally stable and its locking time is very short, the speed of the modified FLL or a PLL is automatically improved. Moreover, besides the speed improvement, all the other performances such as the phase noise (jitter), the bandwidth and the frequency locking range of the modified FLL or a PLL are not altered and are determined only by their basic architectures