MPEG-2 4:2:2@HL encoder chip set

Author

Sato, Hidenori ; Ohira, Hideo ; Kazayama, Masahiko ; Harada, Ayako ; Yoshimoto, Masahiko ; Tanno, Okikazu ; Kumaki, Satoshi ; Ishibara, K. ; Hanami, Atsuo ; Mutsumura, T.

Author_Institution

Inf. Technol. R&D Center, Mitsubishi Electr. Corp., Kamakura, Japan

Volume

4

fYear

2000

fDate

2000

Firstpage

41

Abstract

An MPEG-2 4:2:2@HL encoder chip set will be presented. It is composed of an encoder LSI [COD-LSI], a preprocessor LSI [PP-LSI], and a motion estimation LSI [ME3-LSI]. Scalable architecture allows a cascadable configuration for higher picture quality and higher resolutions. The encoder LSI, which is the key to this chip set, employs advanced hybrid architecture with a 162 MHz media-processor core [D30V] and dedicated video processing hardware. It also has dual-communication-ports for a multi-chip configuration. With above architecture, a single encoder LSI can perform SDTV encoding, and only six chips can perform HDTV encoding

Keywords

high definition television; image resolution; large scale integration; motion estimation; multimedia systems; video coding; 162 MHz; COD-LSI; HDTV encoding; MPEG-2 4:2:2@HL; SDTV encoding; cascadable configuration; dedicated video processing hardware; encoder chip set; hybrid architecture; media-processor core; motion estimation LSI; multi-chip configuration; picture quality; preprocessor LSI; resolution; scalable architecture; Cyclic redundancy check; Discrete cosine transforms; Encoding; HDTV; Hardware; Large scale integration; Motion estimation; SDRAM; Timing; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.858683

Filename

858683