New high performance sub-1 V circuit technique with reduced standby current and robust data holding

This paper describes new high performance and low power circuit technique for the sub-1 V region. Two pairs of depletion transistors are used to construct a self-reverse bias condition for the power source transistors and feedback paths from an output node. They can be fabricated without complicated process changes. New scheme shows drastical suppression of leakage currents by about three orders and safe data holding in the standby mode without sacrificing performance degradation in the active mode and reliability problems