Title :
Hierarchical test coverage
Author_Institution :
Dept. of Res. & Dev., Credence Syst. Corp., Freemont, CA, USA
Abstract :
The IOX productivity enhancement required to produce submicron, System On Silicon (SOS) products will come from high level synthesis and design reuse. SOS products will have an infrastructure which preserves the hierarchical structure of the original conceptual thinking. Time to market and quality goals will require the use of previously created and optimized tests for embedded subsystems. Production tests for embedded subsystems will be abstracted from the hierarchical structure of the SOS product. The solution presented describes a method for encapsulating hierarchical information within a test program. A tester architecture to facilitate hierarchical testing is also presented
Keywords :
high level synthesis; logic design; logic testing; real-time systems; IOX productivity enhancement; SOS products; System On Silicon products; conceptual thinking; design reuse; embedded subsystems; hierarchical information encapsulation; hierarchical structure; hierarchical test coverage; hierarchical testing; high level synthesis; production tests; tester architecture; Automatic test pattern generation; Built-in self-test; Design optimization; Hardware; Integrated circuit synthesis; Manufacturing; Silicon; System testing; Time to market; Timing;
Conference_Titel :
Verilog HDL Conference, 1996. Proceedings., 1996 IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-7431-8
DOI :
10.1109/IVC.1996.496025
