Title :
Matrix approach for fast implementations of logarithmic MAP decoding of turbo codes
Author :
Wang, Duanyi ; Kobayashi, Hisashi
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Abstract :
This paper describes two new matrix transform algorithms for the max-log-MAP decoding of turbo codes. In the proposed algorithms, the successive decoding procedures carried out in the conventional max-log-MAP algorithm are performed in parallel, and well formulated into a set of simple and regular matrix operations, which can therefore considerably speed up the decoding operations and reduce the computational complexity. The matrix max-log-MAP algorithms also maintain the advantage of the general logarithmic MAP like algorithms in avoiding complex numerical representation problems. They particularly facilitate the implementations of the logarithmic MAP like algorithms in special-purpose parallel processing VLSI hardware architectures. The matrix algorithms also allow simple implementations by using shift registers. The proposed implementation architectures for the matrix max-log-MAP decoding can effectively reduce the memory capacity and simplify the data accesses and transfers required by the conventional max-log-MAP as well as MAP algorithms
Keywords :
VLSI; computational complexity; concatenated codes; convolutional codes; interleaved codes; matrix algebra; maximum likelihood decoding; parallel algorithms; turbo codes; VLSI hardware architectures; computational complexity; computational complexity reduction; data access; data transfer; fast implementation; interleaver; logarithmic MAP decoding; matrix approach; matrix max-log-MAP algorithms; matrix max-log-MAP decoding; matrix transform algorithms; max-log-MAP decoding; memory capacity; parallel code concatenation; recursive systematic convolutional codes; shift registers; special-purpose parallel processing VLSI; successive decoding; turbo codes; Circuits; Computational complexity; Computer architecture; Hardware; Iterative algorithms; Iterative decoding; Parallel processing; Shift registers; Turbo codes; Very large scale integration;
Conference_Titel :
Communications, Computers and signal Processing, 2001. PACRIM. 2001 IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-7803-7080-5
DOI :
10.1109/PACRIM.2001.953536