Design of a combined processor containing a 32-bit RISC microprocessor and a 16-bit fixed-point DSP on a chip

In this paper, a combined architecture, YS-RDSP, which merges a RISC microprocessor with a DSP processor to be suitable for embedded applications is proposed and designed. The YS-RDSP can execute maximum 4 instructions in parallel at the same time. In order to reduce the size of programs, the YS-RDSP has variable instruction length of 16-bit and 32-bit. The YS-RDSP provides DSP processing power as well as control power and programmability of RISC microprocessor on a single chip. The YS-RDSP has 8-kbyte ROM and 8-kbyte RAM on chip. System controller which is a peripheral included in the chip provides three power-down modes for low-power operations, and SLEEP instruction switches the operation states of the CPU core and peripherals. The YS-RDSP processor is modeled in Verilog-HDL with top-down design methodology. Verified model is synthesized with 0.6 μm 3.3 V CMOS standard cell library and laid out using automated P&R resulting 10.7 mm by 8.4 mm core area