FPDR90 a low noise, fast pixel readout chip in 90 nm CMOS

We report on the design of a prototype IC called FPDR90 dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPRD90 has dimensions of 4 mm × 4 mm and was designed in CMOS 90 nm technology with 9 metal layers. The core of the IC is a matrix of 40×32 pixels with 100 μm ×100 μm pixel size. Each pixel contains a charge sensitive amplifier (CSA), a main amplifier stage, two discriminators and two 16-bit ripple counters. To minimize the effective threshold spread at the discriminators inputs, one 7-bit and one 6-bit trim DACs are used in each pixel for threshold low and threshold high respectively. The data are read out via a single LVDS output with 200 Mbps rate. Each pixel contains about 1800 transistors and has a static power consumption of 42 μW for nominal bias condition. The effective pulse shaping at the discriminator input is 28 ns and it is mainly determined by the time constants of the CSA. A gain is equal to 32 μV/e^- or 64 μV/e^- in the low and high gain mode respectively. In the high gain mode the ENC without detector is 91 e^- rms and rises to 106 e^- rms with stud bump-bonded pixel detector. The effective threshold spread at discriminator input is only 0.76 mV (at one sigma level, with 7-bit trim DACs enabled), what calculated to the input results in effective spread of about 12 e^- rms.