DocumentCode :
3531327
Title :
Spatial correlation extraction with a limited amount of measurement data
Author :
Whi, Shu-Han ; Su, Bing-Shiun ; Lee, Yu-Min ; Pan, Chi-Wen
Author_Institution :
Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear :
2010
fDate :
3-4 Aug. 2010
Firstpage :
248
Lastpage :
254
Abstract :
With the advance of nanometer technologies, the process variations play important roles in integrated circuit designs. The conventional corner value timing analysis becomes less effective and grossly conservative. Given a limited amount of measurement silicon data and without any distribution assumptions, this work develops a spatial correlation estimation methodology with the bootstrap resampling technique to improve the extraction correctness of the spatial correlation. By constructing the confidence interval of the spatial correlation, the correlation between two path delays can be got, and the high coverage rate for the true spatial path delay correlation has been demonstrated from the experimental results.
Keywords :
integrated circuit design; nanoelectronics; bootstrap resampling; confidence interval; corner value timing analysis; extraction correctness; integrated circuit design; measurement data; nanometer technologies; spatial correlation estimation; spatial correlation extraction; spatial path delay correlation; Data mining; Delay estimation; Fabrication; Gaussian distribution; Integrated circuit measurements; Principal component analysis; Silicon; Testing; Timing; Upper bound;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on
Conference_Location :
Penang
Print_ISBN :
978-1-4244-7809-5
Type :
conf
DOI :
10.1109/ASQED.2010.5548251
Filename :
5548251
Link To Document :
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