A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands

IR drops in a Power Delivery Network (PDN) on chip multi-processors (CMPs) can worsen the quality of voltage supply and thereby affect overall performance. This problem is more severe in 3D CMPs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally to the number of device layers. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent, for instance, each new core mapping on the 3D die will change traffic patterns and have a unique distribution of IR-drops in the PDN. Unfortunately, designers today seldom consider design of PDN while synthesizing NoCs. If NoC synthesis is carried out without considering the associated PDN design cost, it can easily result in an overall sub-optimal design. In this work, for the first time, we propose a novel PDN-aware 3D NoC synthesis framework that minimizes NoC power while meeting performance goals, and optimizes the corresponding PDN for total number of Voltage Regulator Modules (VRMs), current efficiency, and grid-wire width while satisfying IR-drop constraints. Our experimental results show that the proposed methodology provides more comprehensive results compared to a traditional approach where the NoC synthesis step does not consider the PDN costs.