Systolic array implementation of Euclid´s algorithm for inversion and division in GF(2m)

This paper presents a new systolic VLSI architecture for computing inverses and divisions in finite fields GF(2^m) based on a variant of Euclid´s algorithm. It is highly regular, modular, and thus well suited to VLSI implementation. It has O(m²) area complexity and can produce one result per clock cycle with a latency of 8m-2 clock cycles. As compared to existing related systolic architectures with the same throughput performance, the proposed one gains a significant improvement in area complexity