Efficient reduction technique of resistive mesh structured power network

This paper proposes an efficient reduction technique dedicated to a resistive mesh structured power network. The proposed method reduces an uninterested partition of a large mesh structured circuit, which the partition does not contain storage elements, to a simple circuit which consists of resistors and current sources only. The proposed method provides the upper bound of the maximum error of port currents, and can be easily parallelized. In the experimental results, the proposed method showed 10 times faster simulation speed with the average error of node voltage less than 4%.