• DocumentCode
    3532061
  • Title

    Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques

  • Author

    Lv, Jinpeng ; Kalla, Priyank

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Utah, Salt Lake City, UT, USA
  • fYear
    2012
  • fDate
    7-11 Jan. 2012
  • Firstpage
    388
  • Lastpage
    393
  • Abstract
    Finite (Galois) field arithmetic finds applications in cryptography, error correction codes, signal processing, etc. Multiplication usually lies at the core of all Galois field computations and is a high-complexity operation. This paper addresses the problem of formal verification of hardware implementations of modulo-multipliers over Galois fields of the type F2k, using a computer-algebra/algebraic-geometry based approach. The multiplier circuit is modeled as a polynomial system in F2k[x1,x2,⋯,xd] and the verification test is formulated as a Nullstellensatz proof over the finite field. A Grobner basis engine is used as the underlying computational framework. The efficiency of Grobner basis computations depends heavily upon the variable (and term) ordering used to represent and manipulate the polynomials. We present a variable (and term) ordering heuristic that significantly improves the efficiency of Grobner basis engines. Using our approach, we can verify the correctness of up to 96-bit multipliers, whereas contemporary BDDs/SAT/SMT-solver based methods are infeasible.
  • Keywords
    Galois fields; cryptography; error correction codes; formal verification; multiplying circuits; polynomials; signal processing; Galois field multipliers; Grobner basis computations; Nullstellensatz proof; algebraic geometry; computer algebra; contemporary BDD/SAT/SMT-solver; cryptography; error correction codes; finite Galois field arithmetic; formal verification; hardware implementations; high-complexity operation; modulo-multipliers; multiplier circuit; polynomial system; signal processing; Boolean functions; Computers; Data structures; Engines; Integrated circuit modeling; Polynomials; Computer algebra; Finite field; Grobner Bases; Hardware verification;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design (VLSID), 2012 25th International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-4673-0438-2
  • Type

    conf

  • DOI
    10.1109/VLSID.2012.102
  • Filename
    6167783