Design and Implementation of Boundary-Scan Circuit for FPGA

Author

Xie, X.D. ; Li, P. ; Ruan, A.W. ; Li, W.C. ; Li, W.

Author_Institution

Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu

fYear

2009

fDate

28-29 April 2009

Firstpage

1

Lastpage

3

Abstract

Based on the characteristics of FPGA, a boundary scan circuit with an extended instruction set in accordance with IEEE 1149.1 standard has been designed and presented in this paper. The circuit can implement the function of built-in self test (BIST) together with FPGA device-programming. In the design, the architecture of the circuit is simplified by deleting redundant instruction registers and sharing some register chains to save the area. Then the design has been integrated into a FPGA prototype chip and implemented by CSMC 0.5 um DPTM standard CMOS process. The experimental results demonstrate that the boundary-scan circuit has realized the desired function of built-in self test and on-chip programming for the FPGA.

Keywords

CMOS integrated circuits; IEEE standards; boundary scan testing; built-in self test; field programmable gate arrays; instruction sets; integrated circuit design; integrated circuit testing; logic design; system-on-chip; CMOS process; DPTM standard; FPGA; IEEE 1149.1 standard; boundary-scan circuit; built-in self test; circuit architecture; device-programming; instruction set; on-chip programming; size 0.5 mum; Automatic testing; Built-in self-test; Circuit testing; Design for testability; Field programmable gate arrays; Functional programming; Integrated circuit technology; Pins; Prototypes; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-2587-7

Type

conf

DOI

10.1109/CAS-ICTD.2009.4960798

Filename

4960798